CAF (conductive anodic filament) is a conductive filament that grows slowly inside a printed circuit board (PCB) along the gap between glass fiber and resin. Under an electric field and moisture, copper dissolves and is transported, growing from the positive electrode (anode) toward the negative electrode (cathode) until it connects two neighboring holes, causing leakage and intermittent shorts, and in severe cases breaking down the insulation. Because it grows inside the board rather than being a surface residue, even a thoroughly cleaned board is no assurance against it; it has to be controlled through the laminate, hole spacing and the PCB maker’s process, and then verified with IPC’s test method. The order is five steps: recognize the symptoms, ask the PCB maker for laminate and process data, verify with the test method when needed, interpret the results, and then make trade-offs between design, materials and assembly. The key point from public sources: the test method IPC-TM-650 2.6.25 (current version Revision C) uses a 10-layer test board at 65 °C or 85 °C and 87% relative humidity (RH), with DC bias (10 V or 100 V as standard) for 500 hours; a drop in insulation resistance of more than one order of magnitude from the baseline counts as a failure. With the 96-hour stabilization period, the whole test takes about 596 hours.
- Recognize the symptoms first: intermittent leakage, appearing in humid conditions or after the board has sat for a while, with the fault between two neighboring holes, looks more like CAF; if you can see dendrites or residue on the board surface, check the surface first (Stage 1).
- What you need from the PCB maker is detail, not a line saying “no CAF”: the laminate, minimum hole-wall spacing, drilling and hole-wall treatment, and the conditions of the test report (Stage 2).
- Verification takes about 25 days: a 96-hour stabilization period plus 500 hours of bias, a temperature-humidity chamber, a DC bias supply and a meter that can measure very high resistance, and the boards must be cleaned and baked dry first (Stages 3 and 4).
- Prevention lies in design and materials: increase hole-wall spacing and choose laminates with good glass-to-resin adhesion; reflow temperature also has an effect (Stage 5).
This article starts from “the board shows intermittent leakage in humid conditions and CAF is suspected” and ends at “interpreting the test results and deciding the trade-offs in laminate and design.” For whether flux residue needs cleaning, see JIAHON’s published article “Does Flux Residue Need Cleaning? Judging White Residue and a 3-Step Decision”; for how to prove a board is clean after washing, see “How Do You Prove a Board Is Clean? Four Documents to Pass a Customer Audit the First Time”; for whether boards should be baked before assembly, see “PCB Baking: Should Expired Boards Be Baked? A 4-Step Decision Flow.” Leakage caused by surface residue (SIR, surface insulation resistance), the full test conditions of each standard (which must be purchased), and automotive board specifications are outside its scope. Each stage covers how to do it and what public sources say; Stages 1, 3, 4 and 5 also list how JIAHON can help; sources, exceptions and terms are in the notes at the end.
Figure 1. Where CAF grows and why (cross-section illustration). In a side view of the board, between the anode (positive) and cathode (negative), a copper filament grows along the gap between glass and resin, from anode toward cathode, shorting once it connects; moisture forms a water film in the gap (blue ovals are glass fiber cloth, the rest is resin). Hole-wall to hole-wall spacing, together with the voltage difference between the two holes, decides how strong the electric field is. The conditions that must come together: (1) electric field — a potential difference between two neighboring holes; (2) moisture — the board has absorbed moisture and there is a water film in the gap; (3) a path — poor glass-to-resin adhesion leaves a gap; (4) temperature and time — including the high temperature of soldering, and it takes time. It grows inside the board: however clean the surface, that is no assurance against it. It has to be controlled through the laminate, hole spacing and the PCB maker’s process, then verified by testing.
Stage 1: Recognize the symptoms and tell CAF apart from other causes
CAF grows inside the board where it cannot be seen. Narrow it down by the symptoms first, then confirm by reproduction and cross-section.
| What you see | More likely | What public sources say |
|---|---|---|
| Intermittent leakage or shorts | CAF, or surface migration | A public online encyclopedia page (conductive anodic filament): CAF causes current leakage, intermittent shorts and dielectric breakdown between conductors |
| Occurs in humid conditions, or after a period of time | CAF, or surface migration | Same page: humidity, electric field strength and temperature (including soldering temperature) are conditions |
| The fault is between two neighboring holes at different potentials | CAF | Same page: commonly between neighboring vias, along the glass-to-resin interface, growing from anode to cathode |
| Dendrites, white or colored residue visible on the board surface | Surface migration; check the surface first | Same page: CAF grows along the glass-to-resin interface from anode to cathode, inside the board; anything visible on the surface should be investigated as a surface problem first (this article’s synthesis) |
How to do it:
- First write down the fault data clearly: at what voltage, temperature and humidity it occurs; which two nets (sets of connected conductors in the circuit) fail; and whether there is a potential difference between the two nets (this article’s synthesis).
- Check the surface first: is there residue, dendrites or contamination on the board surface? For surface problems, see “Does Flux Residue Need Cleaning?”
- Confirming CAF takes reproduction and cross-section. Methods given on the encyclopedia page: temperature-humidity-bias (THB) testing can reproduce intermittent failures; cross-sectioning (cutting the board open, polishing it and examining it under a microscope) and scanning with a superconducting quantum interference device (SQUID) can help locate the fault.
- Draw a conclusion once the section shows copper along the glass fibers and you have checked that the two holes belong to nets at different potentials (this article’s synthesis).
What public sources say: see the table above.
How JIAHON can help:
- For looking at the board surface and finished cross-sections: 4K 3D digital microscope (the page lists a built-in measurement system and on-screen viewing) and a 40x handheld magnifier (the page lists a folding design with built-in LED lighting).
- For a temperature-humidity chamber to reproduce failures, see Stage 3.
- For pricing and availability, please contact us.
Stage 2: What data to ask the PCB maker for
The board is made by the PCB maker, and CAF risk lies in the laminate and the processes inside the board. A report that just says “passed the CAF test” is not enough; these are the items to ask about.
| What to ask | Why | What public sources say |
|---|---|---|
| Laminate brand and grade, including glass cloth and resin | Poor glass-to-resin adhesion leaves a path for CAF | Encyclopedia page: poor adhesion between resin and glass fiber leaves a CAF path; adhesion may depend on the silane (a surface treatment that helps resin adhere) on the glass fiber. IPC’s test method: the report must list the laminate brand and name or number |
| Minimum hole-wall to hole-wall spacing | Spacing is a design rule; for the same voltage difference, the smaller the spacing, the stronger the field | Encyclopedia page: hole spacing is a design rule for reducing CAF risk. IPC’s test board divides hole-wall spacing into four kinds and reports the failure percentage for each |
| Drilling parameters, desmear and glass etch-back | The report must state them, so you can compare whether the method is the same | The checklist in the appendix of IPC’s test method lists: the drill diameter for each hole spacing, the desmear (removal of resin smear left by drilling) and cleaning process, and whether glass etch-back was used |
| Surface finish, solder mask type, layer count, hole copper thickness, depaneling method, PCB maker and plant location | As above | Same checklist |
| Conditions of the CAF test report: standard and revision, temperature, humidity, bias, time, test board, failure criteria and failure percentage | With different conditions, results cannot be compared | IPC’s test method; conditions in Stage 3 |
How to do it:
- Ask the PCB maker for a CAF test report on “the same laminate with similar hole spacing,” check it against the conditions in the fifth row of the table above, and do not settle for a single word, “passed.”
- Ask again whenever the laminate, process or plant location changes (this article’s synthesis).
- Record the laminate grade, minimum hole spacing and lot number in the part number’s approval documents, so that if it fails later you can trace it (this article’s synthesis).
- If your product has large voltage differences or will be used in humid environments, write the requirements into the purchase specification (this article’s synthesis).
What public sources say: see the table above.
Stage 3: Verify per IPC-TM-650 2.6.25, or have a lab do it
This IPC test method (IPC-TM-650 2.6.25, CAF resistance test in the X-Y axis) is available as a public PDF; the current version is Revision C, document date 02/21. The table below gives the conditions it states; in practice, follow the version you adopt and your customer’s requirements.
| Item | What the method says |
|---|---|
| Purpose | Evaluating laminates, PCB design and use conditions, and process changes; it can also evaluate press-fit connectors |
| Test board | IPC-9253 and IPC-9254 CAF test boards, 10 layers, about 125 × 175 mm (IPC-9254 is an older design superseded by IPC-9253); two sets of structures with hole-wall to hole-wall spacing of 0.27, 0.38, 0.51 and 0.65 mm, and 0.26, 0.37, 0.51 and 0.62 mm |
| Quantity | At least 25 boards per sample lot and per bias level |
| Cleaning | Immersion cleaning per another IPC method (2.3.25) until ionic contamination is below 1.0 µg NaCl equivalent per square centimeter; boards that do not reach this within 20 minutes are scrapped |
| Pre-bake | 105 ± 2 °C for at least 30 minutes |
| Preconditioning | No bias; 23 ± 2 °C, 50 ± 5% RH, at least 30 minutes, after which the first insulation resistance measurement is taken |
| Stabilization | 96 hours (± 30 minutes) at test conditions, without bias |
| Test conditions | 65 ± 2 °C or 85 ± 2 °C; relative humidity 87% +3/−2%; humidity may dip briefly, for no more than 15 minutes each time, provided the chamber air temperature does not exceed the board temperature by more than 5 °C |
| Bias | To compare laminates and processes: 10 VDC and 100 VDC are both standard biases; to reflect actual use: twice the maximum working voltage difference. The supply must deliver 10 to 100 VDC (± 2 V), with at least 1 A of current |
| Time | 500 hours of bias (596 hours including stabilization), which can be extended to 1000 hours or more; measured every 24 to 100 hours |
| Measurement | 100 ± 2 VDC, ramped at 50 V per second, held at least 60 seconds; measurement polarity must match the bias; the meter must measure up to 10^12 ohms (1,000,000 MΩ), with ±5% error at 10^10 ohms |
| Criteria | A drop in insulation resistance of more than one order of magnitude from the baseline (the average at 96 hours) counts as a failure; report the failure percentage for each hole spacing at 500 hours |
| Not counted | Nets below 10 MΩ after stabilization; failures that are not CAF, such as contamination, scratches or cracks; the test may be stopped early if more than half the samples fail |
| Cautions | A 5% difference in relative humidity can change measured resistance by 0.5 to 1.0 orders of magnitude; condensation on the board under bias, or water spots blown by oven air, grow dendrites and must be avoided; the higher the voltage, the faster the failure, and local heating may offset the effect of humidity, so do not go too high; handle boards by the edges, preferably with non-contaminating gloves; keep markings away from biased areas; stand boards upright, at least about 2.5 cm apart |
| Warning | The method states it is not designed for biases above 100 VDC (electric vehicle electronics and the like are often required to be tested at higher voltages); at 100 VDC with a 20 mA cutoff, each channel dissipates 2 watts, so a much lower cutoff current is recommended, which also makes failures easier to analyze |
How to do it:
- Decide the purpose first: to compare laminates and processes, use the standard 10 VDC or 100 VDC bias; to reflect actual use, use twice the maximum working voltage difference (at least 25 boards for each bias level).
- To do it yourself, prepare: a test chamber, a bias supply, a meter that can measure very high resistance, wiring and switching for many nets, and recording; boards must be cleaned and baked first. Stabilization plus bias totals 596 hours, about 25 days, plus the time for cleaning, pre-bake and preconditioning.
- If you would rather not maintain the equipment, commission a lab with CAF capability (this article’s synthesis).
- If the customer specifies an older version, the conditions may differ; follow the version the customer specifies.
What public sources say: see the table above.
How JIAHON can help:
- Test environment: temperature-humidity test chamber (the page lists a 260 L working volume, 0 to 70 °C, 30 to 98% RH, humidity uniformity of ±5% RH, 2 trays and 15 shelf slots as standard, and an optional high-temperature, high-humidity version).
- DC power: DC power supply (the page lists a fixed 24 V output, adjustable from 19.2 to 28.8 V, 27 A rated current, for industrial automation and test instruments).
- Resistance measurement: insulation resistance tester (the page lists test voltages of 50 to 1000 V, with different ranges per setting up to 4000 MΩ; the page positions it for insulation testing of electrical equipment).
- Verifying cleanliness after washing: ionic contamination tester (the page lists measurement with a 3:1 isopropyl alcohol and deionized water extract at a constant 40 ± 1 °C, a real-time display of conductivity and ion concentration curves, and an automatic report when the test finishes).
- Recording temperature and humidity: temperature and humidity data logger (the page lists −25 to 70 °C, 0 to 99% RH, 8,000 records × 2 channels and WiFi transfer).
- Handle boards by the edges without touching the surface: non-powdered latex/NBR finger cots (the page lists four types, including a blue antistatic NBR type, all non-powdered; currently on pre-order).
- Pre-bake: smart programmable oven, see Stage 5.
- For pricing and availability, please contact us.
Stage 4: Interpret the results
What you get from the test is a set of insulation resistance (IR) values over time, plus the appearance and cross-sections of failed boards.
Figure 2. CAF test flow and insulation resistance over time (illustration; curve shapes are illustrative). Flow: clean (until clean enough) → pre-bake (bake out moisture in the board) → precondition (no bias, first measurement) → stabilize (no bias, wait to stabilize) → bias (measure IR periodically) → report (failure percentage per hole spacing). The chart shows insulation resistance (higher is better) against time: the baseline is the value at the end of stabilization, and the failure line is one order of magnitude below the baseline. A passing example stays above the line; a failing example drops below it. Nets that start very low (high-resistance shorts) are not counted. Failure = a drop of more than one order of magnitude from the baseline; what is reported is the failure percentage for each hole spacing. Conditions and criteria follow the version of the standard you adopt.
| What you see | What it may mean | What public sources say |
|---|---|---|
| A net is below 10 MΩ at the end of stabilization | It already had a high-resistance short, not something grown in this test | IPC’s test method: nets below 10 MΩ after stabilization are not counted |
| After bias, resistance drops more than one order of magnitude from baseline | A failure; whether it is CAF still needs confirming | IPC’s test method: a drop of more than one order of magnitude is a failure; failures that are not CAF, such as contamination, scratches or cracks, are not counted |
| Several boards fail at the same hole spacing | The failure percentage is the main result this method reports | IPC’s test method: report the failure percentage for each hole spacing at 500 hours |
| Results differ between the two bias levels | 10 VDC and 100 VDC compare laminates and processes; twice the maximum working voltage difference reflects actual use | IPC’s test method: to compare laminates and processes, 10 VDC and 100 VDC are both standard biases; to reflect actual use, choose twice the maximum working voltage difference |
| Failures concentrated in one laminate, one PCB maker or one lot | Go back to the checklist in Stage 2 | IPC’s test method: the report must list laminate, drilling, desmear, etch-back, surface finish, solder mask, depaneling, layer count and hole copper thickness |
| The same lot of boards gives very different results in different runs | Check chamber humidity, condensation and measurement polarity | IPC’s test method: a 5% difference in relative humidity can make a 0.5 to 1.0 order of magnitude difference; condensation grows dendrites; bias and measurement polarity must match |
| The low-resistance location is at the wiring, not inside the board | Not CAF | IPC’s test method: samples with low resistance at the wiring rather than in the test circuit cannot be used for analysis; to confirm, cut the traces near the test circuit, which destroys the sample |
| Discoloration or corrosion on the surface of failed boards | Possibly a surface insulation resistance failure, not necessarily CAF inside the board | IPC’s test method: after testing, inspect the board surface at 10x for signs of surface insulation resistance failure (such as discoloration or corrosion) |
How to do it:
- Look at the baseline first: each net’s value at 96 hours is the starting point for every later comparison. The method defines the “baseline” in two ways (each board’s own 96-hour average, or the average of non-shorted nets at the same hole spacing); Revision C contains both wordings, so follow your customer’s requirement.
- After a failure, do not look at the resistance value alone: first inspect the board surface with a magnifier or microscope, then section the board to confirm whether copper has grown along the glass-to-resin interface or whether it is contamination, scratches or cracks (this article’s synthesis).
- The result represents “this test board under this set of conditions”; applying it to your product also depends on hole spacing, operating voltage and humidity (this article’s synthesis).
- If the failure percentage is high, go back to the laminate, hole spacing, PCB maker and process lot (against the checklist in Stage 2).
What public sources say: see the table above.
How JIAHON can help:
- For looking at the board surface and sections: 4K 3D digital microscope and 40x handheld magnifier.
- For pricing and availability, please contact us.
Stage 5: Trade-offs in design, materials and assembly
CAF risk runs from design all the way to the use environment, and every part of that has an owner. Look first at which part you control.
Figure 3. Who owns which part (illustration). (1) Design — hole-wall spacing, separating nets with large potential differences, writing requirements into the purchase specification: you control this. (2) Laminate — glass-to-resin adhesion, silane treatment, thermal stability: you specify, the supplier provides. (3) PCB maker’s process — drilling, desmear and etch-back, resin cure: depends on the PCB maker. (4) Assembly and storage — reflow temperature, flux type, cleaning, verification and baking: you control this. (5) Use environment — voltage difference, humidity, time in use: depends on where the product is used. Start with the highest-risk products: large voltage differences, small hole spacing, use in humid environments. Move on design and laminate first; assembly and storage are the other part you can control yourself.
| Approach | Cost or caution | What public sources say |
|---|---|---|
| Increase hole-wall spacing between neighboring holes, or separate nets with large potential differences | Routing density, board area and cost | Encyclopedia page: hole spacing is a design rule for reducing CAF risk; electric field strength is one of the conditions |
| Choose a laminate with better glass-to-resin adhesion | Laminate cost and supply | Encyclopedia page: the laminate, and the silane treatment on the glass fiber, affect adhesion and CAF |
| Lower the reflow temperature and choose a thermally stable laminate | Lead-free solder melts at a high temperature, so lowering it is not easy | Encyclopedia page: temperature (including soldering temperature) is one factor; the approach is this article’s synthesis |
| Incoming boards must be clean; washed boards must be verified | Cleaning equipment and verification time | This article’s synthesis. IPC’s test method: test boards must be cleaned before testing to below 1.0 µg NaCl equivalent per square centimeter |
| Bake before assembly and store in moisture-barrier packaging | Controls moisture uptake before assembly alone and cannot replace hole spacing and laminate design | This article’s synthesis. Encyclopedia page: humidity is one of the conditions |
How to do it:
- Start with the highest-risk products: for products with large voltage differences, small hole spacing or use in humid environments, start with hole spacing and laminate.
- Be clear about who owns which part (Figure 3): design, laminate specification, and assembly and storage are in your control; processes inside the board depend on the PCB maker.
- Before changing laminate, PCB maker, reflow temperature or flux, check the data in Stage 2, and verify per Stage 3 if needed.
- Keep the laminate, hole spacing, lot number, reflow profile, flux, cleaning and verification results in one record (this article’s synthesis).
What public sources say: see the table above.
How JIAHON can help:
- Baking before assembly: smart programmable oven (the page lists nitrogen purging, programmable multi-segment ramp profiles, and several sizes that can be customized). For baking conditions, see “PCB Baking”; for packaging and storage, see “PCBA Moisture-Barrier Packaging: 4 Cases That Need It, and How to Choose Foil Bags.”
- Cleaning equipment: inline PCBA brush cleaner (the page lists water-based and solvent-based models, with roller and disc brushes) and vapor-phase dual-solvent cleaner (the applications listed on the page include precision cleaning of SMT PCBAs). For verifying cleanliness after washing, see the ionic contamination tester in Stage 3.
- For pricing and availability, please contact us.
Related reading
To cover the related process steps, continue with these articles:
- “Does Flux Residue Need Cleaning? Judging White Residue and a 3-Step Decision”
- “How Do You Prove a Board Is Clean? Four Documents to Pass a Customer Audit the First Time”
- “PCB Baking: Should Expired Boards Be Baked? A 4-Step Decision Flow”
- “PCBA Moisture-Barrier Packaging: 4 Cases That Need It, and How to Choose Foil Bags”
- “How Tightly to Control Plant Temperature and Humidity: Which Conditions Matter for Solder Paste, Moist Components and ESD, in 5 Stages from Setting the Window to Audit”
Notes: sources and exceptions
These notes are for readers who want to check the sources; you can follow the steps above without them. Where your customer’s specifications and acceptance criteria differ from this article, they take precedence.
Sources for each practice
| Practice | Content | Source |
|---|---|---|
| Test method and conditions | Test board, cleaning, pre-bake, preconditioning, stabilization, test conditions, bias, time, measurement, failure criteria, items not counted, cautions, variables the report must list | Full text of IPC’s test method IPC-TM-650 2.6.25 Revision C (document date 02/21) |
| CAF mechanism and factors | Definition; the glass-to-resin interface; anode to cathode; factors; THB, cross-section and SQUID; design rules and materials | A public online encyclopedia page (conductive anodic filament) (no date in the page text; page data shows last edited 2026-10-12) |
| JIAHON’s own material | Product pages, published articles | JIAHON product pages and articles |
This describes the general case; individual situations may differ.
Exceptions and limitations
- Nature of the sources: the encyclopedia page is public and anyone can edit it. The IPC test method cited is IPC’s public Revision C (document date 02/21); older versions, other standards and customer specifications may have different conditions. This article does not cover automotive or other industry specifications.
- Where sources differ: the method defines the “baseline” in two ways (see Stage 4).
- This article’s synthesis and recommendations: splitting CAF into five stages (recognize symptoms, ask for data, verify, interpret, trade off); how to write fault data; checking the surface before CAF; after seeing copper in the section, still checking the potential of the two holes; that for the same voltage difference, smaller hole spacing means a stronger field; recording laminate grade, hole spacing and lot number in the approval documents; writing requirements into the purchase specification; deciding the purpose of the test first; commissioning a lab; that results represent this test board and these conditions alone; going back to the checklist when the failure percentage is high; that baking and moisture-barrier packaging cannot replace hole spacing and laminate design; and keeping records in one place.
- Scope: this article does not cover PCB process details or laminate formulations, automotive or other industry specifications, the full test conditions of other standards, SIR testing or conformal coating.
- Equipment and products: specifications are as stated on each product page; the finger cots are currently on pre-order.
This article summarizes the general case. It is not a restatement of any standard, not an endorsement of any vendor, equipment maker or service provider, and not a promise about your product or process. Follow your customer’s specifications, local regulations and your own validation; individual situations may differ.