What QFN spacer paper does
QFN spacer paper is a key consumable in back-end semiconductor packaging, preventing ESD damage from IC-to-IC friction in transit. QFN ICs sit in JEDEC trays that are stacked for shipping; without spacer paper, ICs rub against each other and can generate static pulses strong enough to break down MOSFET gate oxides, causing permanent failure. Spacer paper protects in two ways: physical separation (the sheet keeps parts from rubbing) and an anti-static coating (10⁶–10⁹ Ω surface resistance drains charge slowly).
A JIAHON affiliated company supplies customers throughout Taiwan. This series fits standard JEDEC IC tray dimensions (78 × 258 mm), and size and basis weight can be customized to your trays.
Specifications
| Item | Specification |
|---|---|
| Product type | Anti-static interleaving paper between QFN (Quad Flat No-leads) IC tray layers |
| Basis weight | 1.56 GM/m² (ultra-light, for semiconductor packaging) |
| Standard size | 78 ± 1 mm (W) × 258 mm (L), fits JEDEC standard IC trays |
| Thickness | Per manufacturer specification |
| Material | PE / PET base + anti-static coating |
| Surface resistance | 10⁶ – 10⁹ Ω (dissipative class under ANSI/ESD S541) |
| Anti-static standard | ANSI/ESD S541 (revised from the former EIA-541) |
| Suitable IC types | QFN, QFP, BGA, LGA and other leadless / short-lead packages |
| RoHS / REACH | Compliant (declarations available) |
Specifications are general semiconductor industry ranges; final selection depends on your JEDEC tray size, IC type, shipping conditions and ESD sensitivity class (HBM / MM / CDM), case by case.
Applications
- Between QFN IC tray layers: packaged QFN ICs are placed in JEDEC trays and stacked; a sheet between each layer keeps the solder side of each IC from rubbing against neighboring parts.
- JEDEC tray base liner: a sheet at the bottom of the tray keeps ICs off the tray base and provides a charge dissipation path.
- Inter-plant shipping: along the route from fab to packaging, test and end customer, ICs are loaded and unloaded many times; spacer paper protects throughout the chain.
- Wafer tray liner: for unsawn wafers in transit or storage, between wafers or between wafer and tray, for physical and static separation. This series is sized for IC trays; for wafers we suggest a custom larger size.
Selection guide
| Application | Suggested basis weight | Suggested surface resistance | Notes |
|---|---|---|---|
| Between small QFN / QFP IC tray layers | 1.5 – 2 GM/m² | 10⁶ – 10⁸ Ω | This series fits |
| Between large BGA / LGA IC tray layers | 2 – 3 GM/m² | 10⁶ – 10⁹ Ω | Slightly heavier for larger parts |
| Between wafers (200 / 300 mm) | 3 – 5 GM/m² | 10⁶ – 10⁸ Ω | Custom large round / square |
| Electronic modules / PCBA bulk packing | 10 – 15 GM/m² | 10⁷ – 10⁹ Ω | Heavier to resist crushing |
| Cleanroom-sensitive applications | 1.5 GM/m² (this series) | 10⁶ – 10⁸ Ω | Low-dust, low-shedding coating |
Why QFN ICs get damaged by static in JEDEC trays
Tribocharging: when two dielectric materials (IC mold compound, JEDEC tray plastic, neighboring ICs) rub together, electrons transfer from one to the other and create a potential difference. Even slight vibration that lets a QFN IC slide in a plastic tray can build up hundreds to thousands of volts.
The gate oxide of MOSFETs inside a QFN IC is only 1–3 nm thick and withstands only 5–20 V. Static above the IC’s HBM (Human Body Model) rating can break down the gate oxide and cause permanent failure. If a few ICs in a tray are damaged while the packages look intact, the problem may only show up as abnormal yield for a lot after the customer solders and tests them — and is very hard to trace.
Basis weight and surface resistance are independent
A common selection mistake is to treat basis weight and surface resistance as the same thing, or to assume a heavier sheet protects better. They are separate:
| Property | Meaning | Affects | Range |
|---|---|---|---|
| Basis weight (GM/m²) | Weight per unit area; affects thickness and softness | Physical separation, IC contact risk | 1.5 (ultra-light) / 2–3 (medium) / 10–15 (heavy) |
| Surface resistance (Ω) | Static dissipation, from the anti-static coating formulation | ESD protection class | < 10⁴ (conductive) / 10⁴ to < 10¹¹ (dissipative) / ≥ 10¹¹ (insulative) |
| Thickness (derived) | Set by basis weight and density | Stack height, number of tray layers | Per manufacturer specification |
| Softness | Lighter is softer | Risk of scratching ICs | 1.5 GM/m² suits precision ICs |
Check both together. A stiff 15 GM/m² sheet is not recommended for QFN even if it is dissipative; a soft 1.5 GM/m² sheet that is insulative gives no ESD protection at all. This series (1.56 GM/m² + 10⁶–10⁹ Ω dissipative) matches QFN packaging needs.
ANSI/ESD S541 surface resistance classes for packaging
ANSI/ESD S20.20 is the ESD Association’s standard for ESD control programs; packaging materials are classified by surface resistance under ANSI/ESD S541 (revised from the former EIA-541):
| Class | Surface resistance | Typical materials | Suitable for |
|---|---|---|---|
| Conductive | < 1×10⁴ Ω | Metallized bags (aluminum foil laminate), conductive foam | GaN power devices, high-frequency RF, automotive ICs (with lower HBM ratings) |
| Dissipative | 1×10⁴ to < 1×10¹¹ Ω (this product 10⁶–10⁹ Ω) | QFN spacer paper (this series), anti-static bags, anti-static foam | QFN / QFP / BGA / LGA |
| Insulative | ≥ 1×10¹¹ Ω | Ordinary PE / PP bags, cardboard | Non-ESD-sensitive parts (passives, mechanical parts) |
Why not choose conductive? Conductive materials (< 10⁴ Ω) discharge too fast and can cause a discharge spike the moment they touch an IC, which can itself damage the part. Dissipative materials drain charge slowly to avoid this. Unless the device is extremely sensitive to external electromagnetic interference (such as automotive power ICs or military parts), dissipative is the usual choice for semiconductor packaging.
Storage tips
- Use within 30 days after opening the vacuum moisture-barrier pack: the anti-static coating can absorb moisture and degrade. After 30 days, spot-check surface resistance first and change batches if it is outside 10⁶–10⁹ Ω. In a fab environment (22 °C, 45% RH), 7–14 days is better (general experience; follow the manufacturer’s specification and your conditions).
- For inter-plant shipping, use spacer paper inside the tray plus a metallized bag outside: dissipative spacer paper between each IC layer (against tribocharging), and a conductive metallized bag around the whole tray (against external EMI / EMP). This double protection costs little and covers ESD risks across the shipping chain.
- Documentation: when buying, ask for a surface resistance test report per lot measured to ANSI/ESD STM11.11, and RoHS / REACH declarations. Customer quality audits usually check these.
Standards referenced
- ANSI/ESD S20.20, ESD Control Program — EOS/ESD Association, Inc.
- ANSI/ESD S541, Packaging Materials — EOS/ESD Association, Inc.
- ANSI/ESD STM11.11, Surface Resistance Measurement of Static Dissipative Planar Materials — EOS/ESD Association, Inc.
- RoHS Directive 2011/65/EU — European Commission
- REACH Regulation (EC) No 1907/2006 — European Commission
Related: ESD and packaging products · JEDEC IC trays and accessories · Wafer carriers, liners and shipping consumables
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