Putting a via directly on a pad (via-in-pad) gives a fine-pitch BGA room to route, or lets a QFN thermal pad carry heat to the inner layers. The cost is that when the hole is not handled well, solder is drawn into the hole and the joint is short of solder, and the air in the hole also moves into the joint during reflow and becomes a void.
One public test writes that, under a reflow profile that tends to produce voids, unfilled holes had more voids than filled holes, and larger ones, sometimes up to 5 times; for filled holes, no significant difference in void rate was found against a pad with no hole. IPC-4761 divides via treatment into seven types, and the one commonly used for holes in a pad is filling and then plating over flat; a QFN thermal via can be plugged, or covered with solder mask from the front. Which one to choose is to be discussed with the board maker, and the voids are then checked by X-ray or cross-section.
This article is about whether and how to plug the vias on BGA and QFN pads, and the effect on assembly; high-frequency signals, impedance design, and the board maker’s hole-filling process details are outside its scope. It is divided into 5 stages:
Stage 1 | Know the holes on a circuit board first: plated through-holes, non-plated holes, vias, and why a hole is put on a pad.
Stage 2 | The risks of via-in-pad: solder drawn away, voids, residual chemicals; the effect of voids on reliability depends on the part.
Stage 3 | The seven IPC-4761 treatments: covering, plugging, filling, and filling then plating flat, and what problem each has.
Stage 4 | How to choose for BGA and QFN: the approach for holes on BGA pads and for QFN thermal vias.
Stage 5 | Talking with the board maker and verifying voids: first explain why the treatment is wanted, then check the result by X-ray or cross-section.
Each stage below writes: what to do and what the public sources say, with what Jiahon can help with where there is a match; the sources, exceptions, and compilation are in the “Notes” at the end. This is the general case; individual cases still have to be judged on their own.
Figure 1: The five stages of via-in-pad: know the hole, see the risks, seven treatments, how to choose for BGA and QFN, verify voids (illustration).
Stage 1: Know the holes on a circuit board first
What to do:
Three kinds of holes: the plated through-hole (PTH) for through-hole parts; the non-plated hole (NPTH, for example positioning holes and screw holes); and the via, which just connects one layer to another (our own compilation).
Why put it on a pad: for a fine-pitch BGA, routing out from the pad “dog-bone” style and then drilling leaves too little room; putting a blind microvia directly on the pad and routing from the inner layer lets denser parts be placed (Source 3).
Holes for heat: the thermal pad under a QFN relies on vias to carry heat to the inner layers; whether to drill, and how many, depends on how much heat the part gives off (Source 5).
Good for design, hard to make: via-in-pad helps the design, but at the same time brings problems to both board fabrication and assembly (Source 3).
What the public sources say:
A technical paper from an electronic materials company, placed on the IPC website (Source 3; no year marked, references up to 2001) writes: one limit on keeping a high pin count while shrinking array packages is connecting to the board surface with vias plus dog-bone routing; the alternative is to place a blind microvia on the SMT pad and connect through the inner layers, giving room for chip-scale packages at a finer pitch; via-in-pad helps the design engineer, but brings problems to both board fabrication and assembly.
A QFN and SON soldering application note from a semiconductor company (Source 5; issued June 2002, revised December 2023) writes: not every application needs thermal vias, depending on the power the part dissipates; but the central thermal pad has to be soldered to the board for mechanical strength and reliability (Note Table 1).
Stage 2: The risks of via-in-pad
What to do:
Solder drawn away: when a hole is neither plugged nor covered, solder flows into the hole and the joint that was meant to be made is short of solder (Sources 5, 6).
Air becomes voids: when solder paste is printed, unless the print is deliberately offset, the paste covers the hole on the pad, and the gas in the hole expands during reflow and moves into the joint (Source 3); another paper holds that the dent caused by the hole traps air during printing and it cannot get out during reflow (Source 2).
Unfilled holes have more voids: in one test, under a reflow profile that tends to produce voids, unfilled holes had more voids than filled holes, and larger ones, sometimes up to 5 times; for filled holes, no statistically significant difference in void rate was found against a pad with no hole (Source 2).
Residual chemicals: when the hole is very small it is hard to wet and clean, which leaves corrosive process chemicals and an incomplete surface finish (Source 3); plugging the hole can avoid residue and corrosion, air leaking at ICT, solder balls, and loss of solder paste (Source 1).
The effect depends on the part: in a test by an industry consortium, with lead-free solder paste and temperature cycling, unfilled microvia-in-pad had a negligible effect on a large ceramic BGA with 0.89 mm solder balls, but clearly reduced the life of a BGA with 0.46 mm solder balls and of a 72-contact QFN (Source 4).
What the public sources say:
The paper from the electronic materials company mentioned above (Source 3) writes: with a 100 µm microvia drilled by laser, ordinary conformal plating shrinks the opening by at least half, leaving a finished opening of under 50 µm, which wets poorly and causes residual corrosive chemicals and an incomplete surface finish; in assembly, unless the print is deliberately offset, the solder paste covers the via and traps gas, which expands into the joint during reflow.
A joint paper led by another company of the same group (Source 2; placed on the IPC website, no year marked, citing reports up to 2006) writes: the paper holds that the dent caused by a microvia on a pad traps air during stencil printing and it cannot be fully driven out during reflow; under a reflow profile that tends to produce voids, unfilled holes consistently produced more and larger voids, sometimes 5 times; when the hole was filled, the void rate showed no statistically significant difference from a pad with no hole.
A paper from a high-density packaging user consortium (Source 4; 2011) writes: the effect of an unfilled microvia-in-pad on the temperature-cycling life of lead-free joints depends on the part, being negligible for a large ceramic BGA and clearly worse for small-ball BGAs and QFNs; the authors speculate that the position of a void may matter more than its size (for example, falling on the path of a fatigue crack), but this was not confirmed, and the paper also writes that the percentage of voids was not correlated with the number of cycles to failure (Note Table 2).
Stage 3: The seven IPC-4761 treatments
What to do:
Type I, tenting: no solder mask opening over the hole, the hole is covered with solder mask; the covering film may break on one or both sides, trapping chemicals and even solder inside (Source 1).
Type II, tenting and covering: like Type I with one more layer of solder mask; the author worries that the area over the hole will be higher and affect stencil printing, and does not recommend using it under a BGA (Source 1).
Type III, plugging: the material goes just partly into the hole and does not assure the hole is sealed; trapped air may push the plug out (Source 1).
Type IV, plugging and covering: Type III with one more layer of solder mask, with problems like those of the earlier types (Source 1).
Type V, filling: the material fills the whole hole, leaving no contaminants inside (Source 1).
Type VI, filling and covering: Type V covered with solder mask; the supplier’s goal is to fill completely, and its own standard is a fill of at least 70% (Source 1).
Type VII, filling and plating over flat: Type VI with a layer of copper plated over both sides of the hole to cover it, usually used for via-in-pad or high-density BGAs; special resin and equipment are needed (Source 1).
Single-sided versions mostly not recommended: Types I to IV come in single-sided and double-sided versions, and IPC does not recommend single-sided (Source 1).
Figure 2: The seven IPC-4761 via treatments: from tenting, plugging, and filling to filling and plating over flat (illustration, based on Source 1, not to scale).
What the public sources say:
A column in an electronics manufacturing magazine by a field applications engineer of a circuit board supplier (Source 1; June 2020) writes: IPC-4761 (a design guide for protecting the structure of vias in circuit boards) divides via protection into Types I to VII; Types I to IV come in single-sided and double-sided versions, and IPC does not recommend the single-sided one; the film of Type I tenting may break, trapping chemicals and even solder; for Type II, the height over the hole may affect stencil printing, and the author does not recommend it within a BGA area; Type III is just partly plugged and does not assure sealing, and trapped air may push the plug out; Type V fills the hole and removes contaminants inside; Type VI covers the filled hole with solder mask, and the author’s company accepts a fill of at least 70%; Type VII adds copper plating over both sides of Type VI, usually used for via-in-pad or high-density BGAs, needing special resin and equipment, without which quality is reduced; for Types I to IV used with an immersion tin finish, the author does not recommend them, because residual chemicals may corrode the copper in the hole (Note Table 3).
Stage 4: How to choose for BGA and QFN
What to do:
Holes on a BGA pad: use filling then plating over flat (Type VII); after filling flat the pad is roughly level, and voids are less likely to stick to the pad (Sources 1, 3).
Filling short of full also helps: in a test comparing three plating methods, a formula with a fill of about 96% cut the average void size by 74%, and a formula with a fill of about 59% cut it by 64%; this is just one example (Source 3).
Size and pitch of QFN thermal vias: thermal via pitch about 1.0 mm, drill from 0.3 mm; the smaller the hole, the lower the risk of solder loss (Source 5).
Plug or cover for QFN thermal vias: plugging can remove solder loss; when plugging is too costly, the hole can be covered with solder mask; plugging or covering from the back, air trapped in the hole may increase voids, while covering from the front is less likely to give random voids, and the solder mask for front covering should be 0.1 mm larger than the hole (Source 5).
The surface finish matters too: on an OSP board, leaving the holes uncovered on both sides also gives stable soldering performance (Source 5).
Covering lifts the part: a solder mask cap about 2 mil high lifts the QFN and affects the height of the signal-pin joints; the stencil should avoid the cap, and solder paste should not be printed on top of it (Source 6).
Keep holes away from the edge of a signal-pin pad: unless it is fully covered or plugged with solder mask (Source 6).
Figure 3: How to choose: holes on a BGA pad are filled then plated over flat; QFN thermal vias are plugged or covered from the front (illustration, based on Sources 1, 5, 6).
What the public sources say:
The column from the circuit board supplier mentioned above (Source 1) writes: Type VII is usually used for via-in-pad or high-density BGAs.
The paper from the electronic materials company mentioned above (Source 3) writes: two hole-filling formulas had fill rates of about 96% and 59%, and cut the average void size by 74% and 64%; with no filling, the effect of solder paste and reflow profile on voids was much larger, and after filling the solder paste parameters had very little effect, widening the process window; when the fill was fuller the pad was roughly level, and the share of voids sticking to the pad fell to 20%.
The semiconductor company’s application note mentioned above (Source 5) writes: when the thermal need is high, a thermal via pitch of about 1.0 mm is recommended; by the capability of a typical board maker, drilling from 0.3 mm is recommended, and the smaller the hole the lower the risk of solder loss; plugging can remove solder loss, and when it is not worthwhile the hole can be covered; plugging or covering from the back, trapped air may increase voids; covering from the front is less likely to produce random voids, with the solder mask diameter 0.1 mm larger than the hole; an OSP board without covering also has stable performance.
A QFN white paper from an electronics manufacturing services company (Source 6; June 2011) writes: from the assembly point of view, holes plated flat or plated full work well, and avoid solder flowing into the hole; unfilled plated through-holes are not recommended, and if used the holes should be small; a solder mask cap is about 2 mil high and lifts the QFN; holes should not be placed at the edge of a signal-pin pad unless fully covered or plugged; when covering is used, the stencil should not print solder paste on the cap (Note Table 4).
Stage 5: Talking with the board maker, and verifying voids
What to do:
Talk with the board maker first: there are many ways to treat a via, so first tell the board maker clearly why the treatment is wanted and which factors to avoid, so a way that fits the other design conditions can be chosen (Source 1).
Cost: fully plated small holes cost more; when plugging is not worthwhile, covering can be used instead (Sources 5, 6).
Solder paste and reflow profile: when the hole is unfilled, the effect of the solder paste and the reflow profile is large (Source 3); if the soak time is too long and most of the flux is activated before the solder melts, large voids result (Source 5).
Look at the voids: use X-ray and cross-section to look at the size, count, and position of voids; in that test, X-ray showed less improvement than cross-section, and when a small void was defined as about 2% or more the two were closer (Source 3).
Look at position: the authors of one test speculate that the position of a void may matter more than its size (for example, on the path of a crack), but this was not confirmed; the part, solder ball size, hole diameter, and board thickness all change the result (Source 4).
Verify the first batch: for a new design or a change of board maker, use the first batch of boards to check voids and joints before deciding the approach for mass production (our own compilation).
What the public sources say:
The column from the circuit board supplier mentioned above (Source 1) writes: it is recommended that every circuit board design be discussed with the board maker first, and the more complex the design the more so; by explaining clearly why the treatment is wanted and which factors are wanted or not wanted, the ideal approach can be chosen.
The paper from the electronic materials company mentioned above (Source 3) measured the size, count, and position of voids by cross-section and X-ray, and writes: by cross-section, 76% of joints on unfilled holes had voids, against 39% and 23% for the two kinds of filling; X-ray also showed improvement, but not as much, and when a small void was defined as about 2% or more the two were closer.
The application note mentioned above (Source 5) writes: if the soak time is too long and most of the flux is activated before the solder melts, large voids result.
The consortium paper mentioned above (Source 4) writes: the effect of voids from microvia-in-pad is related to the part type, solder ball size, microvia drill size, and substrate thickness; the authors speculate that the position of a void may matter more than its size, but this was not confirmed (Note Table 5).
What Jiahon can help with:
Jiahon’s engineering department can help look at whether a PCB design is easy to produce, including panelization.
For how to choose a way to inspect BGA joints, see Jiahon’s published article How to inspect BGA solder joints: choosing X-ray, red dye, and cross-section, in 5 stages from simple to deep. For the cross-section view, the 4K 3D Digital Microscope can be used to observe and photograph it (the product page says it has a built-in measurement system and can display with multi-angle rotation, used for solder joint inspection and defect identification).
Notes: sources and exceptions
This is for people who need to check; skipping it does not affect the method above. Where your product specification and the board maker’s and part maker’s specifications differ from this article, go by those.
Where each stage comes from
| Source | Where it is used and where it comes from |
|---|---|
| Source 1 | Stages 2, 3, 4, 5: benefits of plugging, the seven IPC-4761 types, talking with the board maker. A column in an electronics manufacturing magazine by an engineer of a circuit board supplier (iConnect007; maker’s material, June 2020) |
| Source 2 | Stage 2: dents trap air, unfilled holes have up to 5 times the voids, filled holes show no significant difference from no hole. A joint paper led by another company of the same group (IPC E29&S05-2; maker’s material, placed on the IPC website, no year marked, citing up to 2006) |
| Source 3 | Stages 1, 2, 4, 5: why put the hole on the pad, gas pockets, residual chemicals, filling reduces voids, X-ray and cross-section. A technical paper of an electronic materials company (IPC E32&S06-6; maker’s material, placed on the IPC website, no year marked, references up to 2001) |
| Source 4 | Stages 2, 5: effect of unfilled microvia-in-pad on lead-free joint life, void position. A technical paper of a high-density packaging user consortium (IPC E6&S28_02; industry consortium, 2011) |
| Source 5 | Stages 1, 2, 4, 5: pitch and diameter of QFN thermal vias, plugging or covering, OSP, reflow profile. A QFN and SON soldering application note of a semiconductor company (TI SLUA271C; maker’s material, issued June 2002, revised December 2023) |
| Source 6 | Stages 2, 4, 5: plated flat or plated full, no unfilled plated through-holes, cap height, hole position, stencil. A QFN white paper of an electronics manufacturing services company (SMTnet; maker’s material, June 2011) |
| Jiahon material | “What Jiahon can help with”; the scope of help from Jiahon’s engineering department, and the article on how to inspect BGA joints |
Note Table 1 | Why put the hole on the pad
| Item | What the public sources say |
|---|---|
| Routing density | Dog-bone routing leaves too little room for a fine-pitch array package; putting a blind microvia on the pad and connecting from the inner layer (Source 3) |
| Cost | It helps the design, but brings problems to board fabrication and assembly (Source 3) |
| Thermal vias | Not every application needs them, depending on the part’s power; the thermal pad must be soldered on (Source 5) |
Sources: see each row.
Note Table 2 | Risks
| Item | What the public sources say |
|---|---|
| Smaller opening | A 100 µm microvia has an opening of under 50 µm after plating, which wets poorly and leaves chemical residue (Source 3) |
| Gas pocket | Solder paste covers the hole (unless the print is deliberately offset), trapping gas that expands into the joint during reflow (Source 3) |
| Dent | The paper holds that the dent traps air during printing and it cannot get out during reflow (Source 2) |
| Amount of voids | Unfilled holes have more and larger voids, sometimes up to 5 times; filled holes show no significant difference from no hole (Source 2) |
| Life | Lead-free joints: effect negligible on a large ceramic BGA; clearly worse on small-ball BGAs and QFN (Source 4) |
| Benefits of plugging | Avoids residue and corrosion, ICT air leaks, solder balls, and loss of solder paste (Source 1) |
Sources: see each row; the figure of Source 2 analyzed just half of the boards, used a reflow profile that tends to produce voids, and the unfilled group was not tested statistically.
Note Table 3 | The seven IPC-4761 types
| Item | What the public sources say |
|---|---|
| Type I | Tenting; the film may break, trapping chemicals or solder (Source 1) |
| Type II | Tenting and covering; higher over the hole, may affect printing, the author does not recommend it within a BGA area (Source 1) |
| Type III | Partly plugged, does not assure sealing; air may push the plug out (Source 1) |
| Type IV | Type III plus covering; problems like the earlier types (Source 1) |
| Type V | Fills the hole, removing contaminants inside (Source 1) |
| Type VI | Filling and covering; that supplier accepts a fill of at least 70% (Source 1) |
| Type VII | Filling then plating copper flat on both sides; used for via-in-pad and high-density BGAs (Source 1) |
| Single-sided | The single-sided versions of Types I to IV are not recommended by IPC (Source 1) |
Sources: see each row; this is a supplier engineer’s compilation of the standard and the author’s own recommendations (70% is that company’s standard, not an industry standard); for the full text of the standard, go by IPC.
Note Table 4 | Approaches for BGA and QFN
| Item | What the public sources say |
|---|---|
| Effect of filling | Two formulas with fill rates of about 96% and 59% cut the average void size by 74% and 64% (Source 3) |
| Process window | With no filling, the effect of solder paste and profile is large; after filling, the effect is small (Source 3) |
| Thermal vias | Pitch about 1.0 mm, drill from 0.3 mm; the smaller the hole, the less solder loss (Source 5) |
| Plug or cover | Plugging removes solder loss; plugging or covering from the back may increase voids; the solder mask for front covering is 0.1 mm larger than the hole (Source 5) |
| OSP | Leaving the holes uncovered also gives stable performance (Source 5) |
| Plated flat or full | From the assembly point of view the effect is good; unfilled plated through-holes are not recommended (Source 6) |
| Cap | About 2 mil high, lifts the QFN; the stencil avoids the cap (Source 6) |
Sources: see each row.
Note Table 5 | Verification
| Item | What the public sources say |
|---|---|
| Talking with the board maker | Explain clearly why the treatment is wanted and which factors to avoid (Source 1) |
| Cross-section | Unfilled holes: 76% of joints with voids; the two kinds of filling: 39% and 23% (Source 3) |
| X-ray | Shows less improvement than cross-section; closer when small voids are defined as about 2% or more (Source 3) |
| Reflow | If the soak time is too long and most of the flux is activated before the solder melts, large voids result (Source 5) |
| Position | The authors speculate that position may matter more than size, not confirmed; related to the part, solder ball, hole diameter, and board thickness (Source 4) |
Sources: see each row.
Exceptions and limits
What we saw and what we did not see: What this article read is 6 public documents (a magazine column, three technical papers placed on the IPC website, an application note of a semiconductor company, and a white paper of an electronics manufacturing services company). We did not read the full text of the IPC-4761 standard; the description of the seven types comes from a supplier engineer’s column, so go by the full text of the standard.
The stance of the sources: Sources 2 and 3 come from the same group: Source 2 is a joint paper led by a company of that group together with an electronics manufacturing services company and a test laboratory, and the hole-filling chemical used is a product of a company of the same group; Source 3 writes the two hole-filling plating methods as technologies under development, without writing who sells them; Source 1 is a circuit board supplier; Source 5 is a part maker; Source 6 is an electronics manufacturing services company. Source 4 is a joint test by several companies of an industry consortium.
The figures are under specific conditions: the figures 5 times, 74%, 64%, and 76% come from their own test boards, solder pastes, and reflow profiles; 0.3 mm, 1.0 mm, and 0.1 mm are that part maker’s recommendations for its own QFN; if the part, board maker, or solder paste changes, go by your own verification.
The scope of the tests: the test of Source 3 covered a BGA with a 1 mm pitch and at most 300 contacts, with no chip-scale packages; “filling short of full also helps” rests on one of the formulas. The sample of Source 4: 16 boards, 64 pieces of each part (half with the hole in the pad, half without), with one cross-section per part; the QFN got clearly worse, the authors could not find the cause, and could not be sure whether voids shorten life by lying on the crack path.
Years: Sources 2 and 3 carry no year (the references of Source 3 run to 2001, and Source 2 cites a report from 2006), and hole-filling technology has improved since; the ideas can be consulted, but for practice go by the capability of the board maker today.
Our own compilation: the three kinds of holes in Stage 1, “verify the first batch” in Stage 5, and the “how to choose” in Figure 3 are our own compilation; every other sentence can be found in the sources or on Jiahon’s pages.
The scope of Jiahon’s help: “What Jiahon can help with” gives the scope of help from Jiahon’s engineering department and the articles already published on the site.
This article is a summary of the general case. It is not a restatement of standard clauses, nor an endorsement of any one board maker, material supplier, or part maker, nor an assurance for your product and process. Go by your product specification, the specifications of the board maker and the part maker, and your own verification; this is the general case, and individual cases still have to be judged on their own.